cmos sram k6t2008v2m, k6t2008u2m family revision 1.0 november 1997 document title 256kx8 bit low power and low voltage cmos static ram revision history revision no. 0.0 0.1 1.0 remark advance preliminary final history design target initial draft finalize - improved v il (min.) : 0.4v ? 0.6v - erase reverse type package - change speed bin km68v2000 : 70/85ns km68v2000 i, km68u2000 , km68u2000 i : 85/100ns - improved standby current commercial product : 15 m a ? 10 m a industrial product : 30 m a ? 15 m a - increased power dissipation : 0.7w ? 1.0w draft data january 30, 1997 april 7, 1997 november 27, 1997 the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserve the right to change the speci fications and products. samsung electronics will answer to your questions. if you have any questions, please contact the samsung branch office s.
cmos sram k6t2008v2m, k6t2008u2m family revision 1.0 november 1997 256kx8 bit low power and low voltage cmos static ram general description the k6t2008v2m and k6t2008u2m families are fabricated by samsung s advanced cmos process technology. the families support various operating temperature ranges and have various package types for user flexibility of system design. the families also support low data retention voltage for battery back-up operation with low data retention current. features process technology: tft organization: 256kx8 power supply voltage k6t2008v2m family: 3.0v ~ 3.6v k6t2008u2m family: 2.7v ~ 3.3v low data retention voltage: 2v(min) three state output and ttl compatible package type: 32-tsop1-0820f, 32-tsop1-0813.4f pin description name function cs 1 ,cs 2 chip select input oe output enable input we write enable input a 0 ~a 17 address inputs i/o 1 ~i/o 8 data inputs/outputs vcc power vss ground n.c. no connection product family 1. k6t2008v2m family = 50ma product family operating temp erature vcc range speed power dissipation pkg type standby (i sb1 , max) operating (i cc2, max) k6t2008v2m-b commercial (0~70 c) 3.0~3.6v 70/85 ns 10 m a 40ma 1) 32-tsop1-f 32-stsop1-f k6t2008u2m-b 2.7~3.3v 85/100 ns k6t2008v2m-f industrial (-40~85 c) 3.0~3.6v 85/100 ns 15 m a k6t2008u2m-f 2.7~3.3v 85/100 ns functional block diagram a11 a9 a8 a13 we cs2 a15 vcc a17 a16 a14 a12 a7 a6 a5 a4 oe a10 cs 1 i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 a3 32-stsop1 type - forward 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-tsop samsung electronics co., ltd. reserves the right to change products and specifications without notice. a12 precharge circuit. memory array 1024 rows 256 8 columns i/o circuit column select clk gen. row select a0 a1 a2 a4 a5 a7 a6 a3 a8 a9 a10 a11 a13 a15 i/o 1 data cont data cont i/o 8 a14 a16 a17 cs 1 we oe cs 2 control logic
cmos sram k6t2008v2m, k6t2008u2m family revision 1.0 november 1997 product list commercial temperature products(0~70 c) industrial temperature products(-40~85 c) part name function part name function k6t2008v2m-tb70 k6t2008v2m-tb85 k6t2008u2m-tb85 k6t2008u2m-tb10 k6t2008v2m-yb70 k6t2008v2m-yb85 k6t2008u2m-yb85 k6t2008u2m-yb10 32-tsop1 f, 70ns, 3.3v, ll 32-tsop1 f, 85ns, 3.3v, ll 32-tsop1 f, 85ns, 3.0v, ll 32-tsop1 f, 100ns, 3.0v, ll 32-stsop1 f, 70ns, 3.3v,ll 32-stsop1 f, 85ns, 3.3v,ll 32-stsop1 f, 85ns, 3.0v, ll 32-stsop1 f, 100ns, 3.0v, ll k6t2008v2m-tf85 k6t2008v2m-tf10 k6t2008u2m-tf85 K6T2008U2M-TF10 k6t2008v2m-yf85 k6t2008v2m-yf10 k6t2008u2m-yf85 k6t2008u2m-yf10 32-tsop1 f, 85ns, 3.3v, ll 32-tsop1 f, 100ns, 3.3v, ll 32-tsop1 f, 85ns, 3.0v, ll 32-tsop1 f, 100ns, 3.0v, ll 32-stsop1 f, 85ns, 3.3v,ll 32-stsop1 f, 100ns, 3.3v,ll 32-stsop1 f, 85ns, 3.0v, ll 32-stsop1 f, 100ns, 3.0v, ll functional description 1. x means don t care (must be in high or low states) cs 1 cs 2 oe we i/o mode power h x 1) x 1) x 1) high-z deselected standby x 1) l x 1) x 1) high-z deselected standby l h h h high-z output disabled active l h l h dout read active l h x 1) l din write active absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.5 to v cc +0.5 v - voltage on vcc supply relative to vss v cc -0.3 to 4.6 v - power dissipation p d 1.0 w - storage temperature t stg -65 to 150 c - operating temperature t a 0 to 70 c k6t2008v2m- l, k6t2008u2m- l -40 to 85 c k6t2008v2m-p , k6t2008u2m-p soldering temperature and time t solder 260 c, 10sec(lead only) - -
cmos sram k6t2008v2m, k6t2008u2m family revision 1.0 november 1997 recommended dc operating conditions 1) note: 1. commercial product : t a =0 to 70 c, otherwise specified industrial product : t a =-40 to 85 c, otherwise specified 2. overshoot : vcc+3.0v in case of pulse width 30ns 3. undershoot : -3.0v in case of pulse width 30ns 4. overshoot and undershoot are sampled, not 100% tested. item symbol product min typ max unit supply voltage vcc k6t2008v2m family k6t2008u2m family 3.0 2.7 3.3 3.0 3.6 3.3 v ground vss all family 0 0 0 v input high voltage v ih k6t2008v2m , k6t2008u2m family 2.2 - vcc+0.3 2) v input low voltage v il k6t2008v2m , k6t2008u2m family -0.3 3) - 0.6 v capacitance 1) (f=1mhz, ta=25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics 1. k6t2008v2m family = 50ma 2. industrial product = 15 m a item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs 1 =v ih or cs 2 =v il or oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a operating power supply i cc i io =0ma, cs 1 =v il , cs 2 =v ih, v in =v ih or v il , read - 2 5 ma average operating current i cc1 cycle time=1 m s, 100%duty, i io =0ma, cs 1 0.2v, cs 2 3 vcc-0.2v, v in 0.2v or v in 3 v cc -0.2v read - 2 5 ma write - 10 15 i cc2 cycle time=min, 100% duty, i io =0ma, cs 1 =v il , cs 2 =v ih, v in =v ih or v il - 30 40 1) ma output low voltage v ol i ol =2.1ma - - 0.4 v output high voltage v oh i oh =-1.0ma 2.2 - - v standby current(ttl) i sb cs 1 =v ih , cs2=v il , other inputs=v ih or v il - - 0.3 ma standby current(cmos) i sb1 cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v or cs 2 0.2v, other inputs=0~vcc - 0.2 10 2) m a
cmos sram k6t2008v2m, k6t2008u2m family revision 1.0 november 1997 ac characteristics ( k6t2008v2m family: v cc =3.0~3.6v, k6t2008u2m family: v cc =2.7~3.3v commercial product: t a =0 to 70 c, industrial product: t a =-40 to 85 c) parameter list symbol speed bins units 70ns 85ns 100ns min max min max min max read read cycle time t rc 70 - 85 - 100 - ns address access time t aa - 70 - 85 - 100 ns chip select to output t co1 , t co2 - 70 - 85 - 100 ns output enable to valid output t oe - 35 - 40 - 50 ns chip select to low-z output t lz 10 - 10 - 10 - ns output enable to low-z output t olz 5 - 5 - 5 - ns chip disable to high-z output t hz 0 25 0 25 0 30 ns output disable to high-z output t ohz 0 25 0 25 0 30 ns output hold from address change t oh 10 - 15 - 15 - ns write write cycle time t wc 70 - 85 - 100 - ns chip select to end of write t cw 60 - 70 - 80 - ns address set-up time t as 0 - 0 - 0 - ns address valid to end of write t aw 60 - 70 - 80 - ns write pulse width t wp 55 - 60 - 70 - ns write recovery time t wr 0 - 0 - 0 - ns write to output high-z t whz 0 25 0 30 0 30 ns data to write time overlap t dw 30 - 35 - 40 - ns data hold from write time t dh 0 - 0 - 0 - ns end write to output low-z t ow 5 - 5 - 5 - ns c l 1) 1. including scope and jig capacitance ac operating conditions test conditions (test load and input/output reference) input pulse level: 0.4 to 2.2v input rising and falling time: 5ns input and output reference voltage:1.5v output load(see right): c l =100pf+1ttl data retention characteristics 1. cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v( cs 1 controlled) or cs 2 0.2v(cs 2 controlled) item symbol test condition min typ max unit vcc for data retention v dr cs 1 1) 3 vcc-0.2v 2.0 - 3.6 v data retention current i dr commercial industrial vcc=3.0v cs 1 3 vcc-0.2v cs 2 3 vcc-0.2v or cs 2 0.2v 0.2 10 15 m a data retention set-up time t sdr see data retention waveform 0 - - ms recovery time t rdr 5 - -
cmos sram k6t2008v2m, k6t2008u2m family revision 1.0 november 1997 address data out previous data valid data valid timming diagrams timing waveform of read cycle(1) (address controlled , cs 1 = oe =v il , we =v ih ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) data valid high-z cs 1 address oe data ou t notes (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. cs 2 t oh t aa t olz t lz t ohz t hz(1,2) t rc t co2 t oe t co1
cmos sram k6t2008v2m, k6t2008u2m family revision 1.0 november 1997 timing waveform of write cycle(1) ( we controlled) address cs 1 t cw(2) t wr(4) timing waveform of write cycle(2) ( cs 1 controlled) address cs 1 t wc t wr(4) t as(3) cs 2 t cw(2) t wp(1) t dw t dh t ow t whz data undefined data valid we data in data out t dw t dh data valid we data in data out high-z high-z cs 2 t wc t aw t as(3) t cw(2) t wp(1) t aw
cmos sram k6t2008v2m, k6t2008u2m family revision 1.0 november 1997 data retention wave form cs 1 controlled v cc 3.0/2.7v 1) 2.2v v dr cs 1 gnd data retention mode cs 1 3 v cc - 0.2v t sdr t rdr timing waveform of write cycle(3) (cs 2 controlled) address cs 1 t aw notes (write cycle) 1. a write occurs during the overlap of a low cs 1 , a high cs 2 and a low we . a write begins at the latest transition among cs 1 goes low, cs 2 going high and we going low : a write end at the earliest transition among cs 1 going high, cs 2 going low and we going high, t wp is measured from the begining of write to the end of write. 2. t cw is measured from the cs 1 going low or cs 2 going high to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr1 applied in case a write ends as cs 1 or we going high t wr2 applied in case a write ends as cs 2 going to low. cs 2 t cw(2) we data in data valid data out high-z high-z t cw(2) t wr(4) t wp(1) t dw t dh t as(3) t wc cs 2 controlled v cc 3.0/2.7v 1) 0.4v v dr cs 2 gnd data retention mode t sdr t rdr 1. 3.0v for k6t2008v2m family, 2.7v for k6t2008u2m family. cs 2 0.2v
cmos sram k6t2008v2m, k6t2008u2m family revision 1.0 november 1997 32 pin thin small outline package type i (0820f) #32 1.00 0.10 0.039 0.004 max 8.40 0.331 0 . 1 0 m a x 0 . 0 0 4 m a x #1 0.50 ( ) 0.020 18.40 0.10 0.724 0.004 0.45 ~0.75 0.018 ~0.030 20.00 0.20 0.787 0.008 #17 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 #16 package dimensions units: millimeter s (inch es ) 32 pin smaller thin small outline package type i (0813.4f) 1.00 0.10 0.039 0.004 max 8.40 0.331 1 . 1 0 m a x 0 . 0 0 4 m a x #1 0.50 ( ) 0.020 11.80 0.10 0.465 0.004 0.45 ~0.75 0.018 ~0.030 13.40 0.10 0.528 0.008 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 #16 #32 #17
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